发明名称 |
Semiconductor memory having bit lines with isolation circuits connected between redundant and normal memory cells |
摘要 |
A semiconductor memory system in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available for each of a plurality of sub-arrays of a normal memory. |
申请公布号 |
US5022006(A) |
申请公布日期 |
1991.06.04 |
申请号 |
US19880175883 |
申请日期 |
1988.04.01 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
FIFIELD, JOHN A.;TOMASHOT, STEVEN W. |
分类号 |
G11C11/413;G11C11/401;G11C29/00;G11C29/04 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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