| 摘要 |
A bidirectional variable bit shifter (10) is disclosed which comprises a latch/input driver (12) coupled to a word shift array (14) coupled to a nibble shift array (16) coupled to a bit shift array (18) coupled to a latch/output driver (20). The bidirectional variable bit shifter (10) further comprises three sense amps (24, 26, 28) coupled to the word, nibble and bit shift arrays (14, 16, 18) respectively, and the outputs of the three sense amps (24, 26, 28) are coupled to the input of a logic-OR gate (30) which has as its output an Indicator Bit signal. The word, nibble and bit shift arrays (14, 16, 18) are coupled to control decode circuit (22) which receives and decodes information from a Microcode Control Bus and from three shift count control buses. Parallel data bits are input to the bidirectional variable bit shifter (10) through the latch/input driver (12), and shifted 0, 16, 32, 48, 64 or 80 bits by the word shift array (14), 0, 4, 8, or 12 bits by the nibble shift array (16), and 0, 1, 2 or 3 bits by the bit shift array (18). The word, nibble and bit shift arrays (14, 16 and 18) send signals to the sense amps (24, 26, 28) respectively when significant data bits are shifted right of the least significant bit on right shift operations which in turn signal logic-OR gate (30). The control decode circuit (22) controls the direction of shfits, the number of bit positions shifted, and the fill node within the word, nibble and bit shift arrays (14, 16, 18).
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