CHARGING AND EQUALIZING CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE

摘要

In circuit for charging and lighing a bit-line of static ramdom acess memory (SRAM), charging circuit is composed of the first and the second P-MOS transistors (31,32) connected dircctly to between a driving voltage and bit-line. Output purse of address transition detector (ATD) is applied to the gate of these transistors. Lighting circuit includes the third P-MOS transistor (33) connected with parallel to the two terminals of bit-line. Loading circuit is composed of the fourth and the fivth transistors (34,35) connected with parallel to the each of charging circuit.