| 摘要 |
<p>In a source-coupled FET logic type output circuit, the drain electrodes of first and second FETs (Q1, Q2) are coupled through a level shift element (LS1) to a high-voltage power source (VDD) and load elements (LD1, LD2), the gate electrodes of the FETs are respectively connected to first and second input terminals (IN, IN), and the source electrodes of these transistors which are coupled together are coupled to a low-voltage power source (VSS) by first constant-current power source (CC1). Furthermore, between the high-voltage power source (VDD) and the low-voltage power source (VSS) are connected, third FET (Q3) with its gate electrode coupled to the drain electrode of first FET (Q1), level shift elements (LS2, LS3), second constant- current power source (CC2), fourth FET (Q4) with its gate electrode coupled to the drain electrode of second FET (Q2), level shift element (LS4), third constant- current power source (CC3), fifth FET (Q5) with its gate electrode coupled between fourth FET (Q4) and level shift element (LS4), sixth FET (Q6) with its gate electrode coupled between third level shift element (LS3) and second constant-current power source (CC2), and fifth level shift element (LS5). An output signal with the potential corresponding to that of a complementary signal inputted to the input terminal (IN, IN) to cause the third through sixth FETs (Q3, Q4, Q5, Q6) to perform a push-pull function is obtained at an output terminal (OUT) expending from a connection point between the fifth and sixth FETs (Q5, Q6).</p> |
