| 摘要 |
<p>PURPOSE:To reduce clock skew in a clock synchronization system and to quicken the system by making the wired distance between one clock generating source and each clock skew adjustment circuit nearly equal to each other. CONSTITUTION:A clock generating circuit 1 is provided in the middle of an LSI chip A. Moreover, 4 clock skew adjustment circuits 2 are provided with nearly equal distance from the clock generating circuit 1 and a reference clock MCK as frequency information and a comparison clock REF as phase informa tion resulting from frequency-dividing the reference clock MCK by 1/16 are fed respectively from the clock generating circuit 1 to each clock skew adjust ment circuit 2. Thus, clock skew is reduced in the system in which the inside of the LSI is operated synchronously with the clock and the system speed is quickened.</p> |
