| 摘要 |
PURPOSE:To attain high speed operation of a cell synchronization circuit and to facilitate circuit integration by applying pipeline processing to the CRC(cyclic redundancy check) operation. CONSTITUTION:A CRC arithmetic means has exclusive OR circuit networks 11, 13 dividing an input data 100 into plural number in the order of input and obtaining a residual in parallel with them by a generation polynomial as plural CRC partial arithmetic means. Then a latch circuit 12 and an exclusive OR circuit network 14 are provided, which processes outputs of the plural CRC partial arithmetic means in the order of input and obtains the residual by the generation polynomial as to the entire data series and the CRC operation is realized by the pipeline system. Thus, the parallel processing number is selected properly to realize a cell synchronization circuit at a desired operating speed regardless of 1-bit immediate shift form. Moreover, in the case of LSI processing, since the plural exclusive OR networks applying the plural CRC partial arithmetic operations are of the same constitution, the design of the LSI is facilitated. |
