| 摘要 |
<p>PURPOSE:To relay accurately a frame of a variable length packet architecture in real time by counting number of transmission data at a transmission counter in parallel while receptoin data is being inputted and making the number of transmission data coincident with the number of reception data. CONSTITUTION:When reception data is inputted to a demodulator 10, it is demodulated to an FIFO circuit 30, where the data is latched. The demodulator 10 generates a reception clock ckl at the same time, a reception counter 51 starts counting, data latched in the FIFO circuit 30 is read and inputted to a modulator 20, the transmission is started and a transmission counter 52 starts counting a transmission clock ck2 at the same time. When the reception data is finished, the reception counter 51 stops counting. The transmission counter 52 continues counting in this case and when the count number is coincident with the final count number, an output signal of a comparator 53 is made active, the signal closes the transmission gate 54 thereby stopping the transmission of the transmission data.</p> |
