| 摘要 |
PURPOSE:To process and transmit a data signal at a high speed accurately by providing a data hold means between respective signal processing circuits and after a signal processing circuit of the final stage respectively and supplying a same clock signal to the plural signal processing circuits and the plural data hold means. CONSTITUTION:A data input terminal A connects to plural input terminals of a signal processing circuit P1, and a latch circuit L1 latching tentatively a data signal connects to an output terminal of the signal processing circuit P1, and then a signal processing circuit P2 and a latch circuit L2 are connected thereafter. The signal processing circuit and the latch circuits are used as a pair and n-set of the pairs are connected in series and the latch circuit Ln of the final stage is connected to a data output terminal B. Moreover, the signal processing circuits P1-Pn and the latch circuits L1-Ln are connected to a clock input terminal CK receiving a clock signal to operate them synchronizingly. Thus, a data signal is processed and sent at a high speed accurately. |
