| 摘要 |
<p>PURPOSE:To correct the design disaccord due to the variance of LSI elements on production in real time by detecting timing of output signals from an internal circuit to plural signal lines and matching the timing of output signals to one another through variable capacitance means. CONSTITUTION:Timing of output signals outputted from an internal circuit 11 to plural signal lines L are detected by a detecting means 14. A variable capacitance means 12 of each signal line L is controlled through a control means 13 based on detected results to perform such control that timing of respective output signals electrically coincide with one another, and the design disaccord due to the variance of LSI elements on production is corrected in real time to shorten the LSI development time.</p> |
