| 摘要 |
PURPOSE:To prevent delay of the transition time of an output signal by providing a field effect transistor whose source-drain path is connected between a second power supply terminal and the output terminal, to which gate terminal a logic signal with a phase reverse to the logic level of an output terminal is impressed. CONSTITUTION:The source of a P channel MOS field effect transistor Q5, is connected to the power supply terminal 3, the drain is connected to the output terminal 4, the back gate is connected to the power supply terminal 3 and the gate terminal is connected to a logic signal in a step preceding to a phase division transistor Q1 which logic phase is reverse to the output. When the level of the output terminal 4 is 'L', a level 'H' is impressed to the gate input terminal of the P-MOS transistor Q5. In such a state, when the signal of 'H' to 'L' is inputted to the base of the phase division transistor Q1, namely, to the input terminal, the level of the collector is changed from 'L' to 'H'. At such a time, even when the potential of the output terminal 4 is close to VOH, the output potential is increased to a power supply voltage VCC as shown by (b) by a P-MOS transistor Q3. Accordingly, a logic circuit can arrive at a potential close to the VOH earlier than a conventional circuit by delta (t). |
