发明名称 Voltage level translation circuit.
摘要 <p>The invention provides a static inverter-type TTL/CMOS level translator including transistors (Q2 & Q5) to suppress hot electron effects. The transistors limit maximum VDS to VCC-VTN at the first and second gain stages. Resistors (R1 & R2) serve as a virtual VCC modulator to minimize voltage variations, stabilizing the VIL/VIH trip point. The resistors (R1 & R2) also minimize standby current so that the translator can be used in a low standby current environment. The translator provides faster speed, wider process margins, better reliability and lower standby current than prior art translators.</p>
申请公布号 EP0417895(A2) 申请公布日期 1991.03.20
申请号 EP19900308180 申请日期 1990.07.25
申请人 SAMSUNG SEMICONDUCTOR, INC. 发明人 CHANG, SHUEN-CHIN
分类号 H03K19/0185;H03K19/003 主分类号 H03K19/0185
代理机构 代理人
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