发明名称
摘要 PURPOSE:To increase stored electric charge in a capacitive element of a MOSRAM cell and make the element smaller by a method wherein three or more conductive layers are formed on a thick selectively oxidized film with insulation layers in between and every other conductive layers are connected together. CONSTITUTION:In the case of, for instance, a n-channel 1 transistor type RAM, three phosphorus doped Si layers 5, 7, 12 are formed and piled with insulation films 6, 11 in between. The layer 5 and the layer 12 are connected together and compose a capacitive element with the layer 7. One electrode, for instance, the layer 7 (or the layer 5), of the capacitive element is connected to a n<+> diffused layer 2 to be used as a charge storing electrode and another electrode, for instance, the layer 5 (or the layer 7), is used as a grounding electrode. With above configuration, if the occupied area is the same as the conventional cell, the charging capacity can be increased and the large read out signal can be obtained, so that the malfunction can be avoided. If the capacity is the same as the conventional cell, the dimensions of the said cell can be decreased.
申请公布号 JPH0320905(B2) 申请公布日期 1991.03.20
申请号 JP19800187295 申请日期 1980.12.29
申请人 FUJITSU LTD 发明人 SHIOTANI YOSHIMI;NAKAMURA MICHIO
分类号 H01L27/10;H01L21/822;H01L21/8242;H01L27/04;H01L27/108 主分类号 H01L27/10
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