| 摘要 |
PURPOSE: To ensure the reliable operation by comparing the sign associated with the evaluation cycle of each hardware with the sign associated with the evaluation cycle of previous apparatus. CONSTITUTION: A pattern is applied by the oscillator of a clock controller 11, and continuously recorded. The sign is updated until the address comparison generates a 'next last sign ready' signal is generated. If it is now synchronized with a normal pattern cycle, sign comparison 23 is enabled to compare the previous apparatus evaluation cycle stored in a register clock 22 with the present sign of a shift register clock 21. If it is not accurately compared, an error counter is incrementally increased. If the count is smaller than or equal to the retried register count of the register, the controller 11 again automatically restarts the evaluation. If it is larger, a fault signal is returned to a simulation program, and the evaluation cycle is finished. |
