发明名称 LOCK/UNLOCK DETECTION CIRCUIT FOR PLL CIRCUIT
摘要 PURPOSE:To improve the reliability of the VTR system by latching an output clock of a PLL circuit generating a clock synchronously with a reproduction data. CONSTITUTION:A signal recorded on a magnetic tape 1 is reproduced by a magnetic head 2, the frequency characteristic of a tape head system is corrected by a reproduction equalizing circuit 3 and a binary signal A is obtained. A pulse B having a pulse width corresponding to a half the pulse interval of the reproduction data is generated by a pulse generating circuit 4 at the leading and trailing of the signal A. When the clock C generated from a PLL circuit 11 is latched by the pulse B, the latch output is processed according to the request of the entire system of the digital VTR and used for alarm information or the like. Thus, a fault location when a fault takes place is limited, quickly and the operation with high reliability is attained.
申请公布号 JPH0360291(A) 申请公布日期 1991.03.15
申请号 JP19890194115 申请日期 1989.07.28
申请人 HITACHI LTD 发明人 UMEMOTO MASUO
分类号 H04N5/92;H03L7/095;H04N5/7826 主分类号 H04N5/92
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