| 摘要 |
PURPOSE:To reduce the interference noise of inter-bit by adding transistors to sense amplifier circuits connected to a memory cell array in serial and supplying a potential which is sufficiently lower than a power voltage to gates. CONSTITUTION:The third transistors Tr00, Tr01... are provided in serial for the sense amplifier circuits SA0, SA1... consisting of two transistors Tr10, Tr20, Tr11, Tr21.... For operating them in saturated areas, the same gate voltage 10 is impressed on the gates of respective third transistors Tr00, Tr01.... The potentials of respective pairs of bit lines drop by a prescribed current which is controlled at that time and the signals of the bit lines BL0 and BL1 are amplified. Consequently, time when all the sense amplifier circuits SA0 and SA1 start operating becomes almost constant. Thus, interference noise between adjacent bit lines owing to the connection capacity of inter-bit line can be prevented. |
