发明名称 |
LINE SPEED DETECTION SYSTEM |
摘要 |
<p>PURPOSE:To discriminate a normal character data speed in succession to a speed detection character by allowing a line speed detection means to calculate the line speed when a detection means detects a prescribed number of rising or falling. CONSTITUTION:A rising or falling detection circuit 10 detects the rising or falling of a speed detection character sent from a reception signal line. A clock circuit 40 gives a clock signal of a prescribed period to the circuit 10 in this case to calculate the rising or falling time. The rising or falling and time information is stored in a rising or falling storage circuit 50 and used to reproduce the speed detection character as a normal character. When a speed calculation circuit 20 based on a prescribed logic designated by the line offer company detects a prescribed number such as 2 of rising or falling, the circuit 20 calculates immediately the line speed by using the time information from the circuit 40.</p> |
申请公布号 |
JPH0357349(A) |
申请公布日期 |
1991.03.12 |
申请号 |
JP19890191542 |
申请日期 |
1989.07.26 |
申请人 |
FUJITSU LTD;KOKUSAI DENSHIN DENWA CO LTD <KDD> |
发明人 |
SONE YUKIO;SATO TATSUO;NISHIYAMA YOICHI |
分类号 |
H04L29/08;H04L7/04 |
主分类号 |
H04L29/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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