| 摘要 |
PURPOSE:To accurately detect overflow by calculating one high-order bit excessively in the process of computation by shifting an cumulative partial product rightward by one bit. CONSTITUTION:The multiplier is provided with a shift number arithmetic controller 4a which performs the control of the number of shift of a barrel shifter 7 and that of a comprementer 8, a one-bit shifter 11 which performs one-bit right shift only in initial computation and no shift in order cases, an LSB flag 12 which holds the overflow in right shift, and an overflow detection circuit 13 setting a carry C4 from 2<4> of an adder 9, a carry C5 from 2<5>, the most significant bit of the output of the adder, and the overflow bit of the barrel shifter as input. By performing the one-bit right shift of the cumulative partial product in the initial computation, and adding a number in which the partial product is further shifted by one bit rightward, the cumulative partial product with the number of digits less than a true value by one bit is generated, and the least significant bit can be decided after computation. In such a way, the overflow can be accurately detected by detecting the overflow of the barrel shifter and that of the adder. |
