| 摘要 |
The generator uses one resistor and capacitor to generate a number of reset signals for initial conditioning of the IC logic circuit so that the surface for the resistor and capacitor in the IC can be reduced. Also it provides the right initial timing value to each logic circuit for stabilising the initial oscillation. The generator comprises a generator providing the reset signal having uniform initial time constant, a counter providing delayed signals by counting the synchronous signals of the system and digital logic circuit, a decoder decoding the counter output, a latch latching the generator output by the decoder output, and a generator providing the reset signals having various time differences.
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