发明名称 FRAME SYNCHRONIZING SIGNAL DETECTOR
摘要 PURPOSE:To easily and programmably set the number of bits of a frame synchronizing signal and a frame synchronizing condition, etc., by performing the processing of serial data synchronously with the frame synchronizing signal after detecting the frame synchronizing signal from serial data. CONSTITUTION:A sub-CPU 7 which receives demodulated data at every bit retrieves a frame synchronizing signal having preliminarily determined bit length and bit pattern from this data. At this time, the bit length and the bit pattern of the pertinent frame synchronizing signal can be arbitrarily set and programmed. In the case of receiving the instruction of reception start, a serial I/O 3 starts the reception of data from an MSK MODEM 9 and transfers received data to a main CPU 1 at every 8 bits. The main CPU 1 analyzes the received data to perform the data processing such as the storage of required data to a memory.
申请公布号 JPH0346840(A) 申请公布日期 1991.02.28
申请号 JP19890183131 申请日期 1989.07.15
申请人 TOYO COMMUN EQUIP CO LTD 发明人 KOZAI YOSHIMI;MAJIMA SHOZO
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
代理机构 代理人
主权项
地址