| 摘要 |
PURPOSE:To easily build in a scan path without taking clock skew into consideration by using first and second phase clocks different in phase in the scan path test method of, especially, a gate array type semiconductor integrated circuit having a test circuit. CONSTITUTION:Flip flops in plural blocks into which a circuit is divided are connected in series, and a shift path is provided through which the same clock signal is supplied to clock inputs of flip flops in the same block, and the longer delay time is given to the shift path of the block having the larger number. The first phase clock (CLA) and the second phase clock (CLB) opposite in phase which are inputted to clock input terminals 2 and 3 are used to set DI, which is inputted from a data input terminal 1 from blocks 4, 5, 6, and 7, to flip flops 9, 10 to 15, and 16 in blocks. By such constitution, data passing-through due to clock skew does not occur in any block. |
