| 摘要 |
<p>PURPOSE:To receive a high speed data economically by dividing a signal width of a system clock signal in a system into 4 phases and setting a phase at which a middle part of a reception data is retrieved. CONSTITUTION:A 4-phase generating section 1 receives a 4MHz system clock signal CK4T and a 8MHz clock signal CK8T of a double speed, generates and outputs 4HMz split clock signals CX4A-CX4D having 4 equally split phase differences. A switching control section 3 presets one split clock signal to each of the 4 phases TAB-TDA and outputs split clock signal information set by the phase information inputted from a phase detection section 2 as a split clock selection signal SCLK to a selector 4. A latch section 5 receives an input data HRCD giving a prescribed delay to a reception data RCD and outputs a data in synchronism with the pulse of the split clock signal sent by the selector 4. Thus, a fast speed data is economically received.</p> |
