发明名称 |
DETECTING CIRCUIT FOR MEMORY BACK-UP VOLTAGE |
摘要 |
<p>PURPOSE:To prevent the malfunction of a detecting circuit and to evade the reduction and the waste of the current capacity of a memory back-up power supply by using a CMOS gate which works with the memory back-up power supply when the power voltage drops less than the working voltage level of a voltage monitor bipolar IC. CONSTITUTION:A CMOS gate 7 monitors the voltage VDD of a power supply 1 and has an output of a ground potential GND level when the voltage VDD less than a prescribed voltage level is inputted to a bipolar IC 4 which instructs the action of a memory load 2. Then the gate 7 works with a memory back-up power supply 6. The output of the gate 7 is also set at a GND level and both an npn transistor TR 5 and a pnp TR 3 are completely turned off. Thus no current leaks out of the power supply 6 and the reduction and the waste can be prevented for the current capacity of the power supply 6. At the same time, the output of the IC 4 is stabilized and the malfunctions of a detecting circuit for memory back-up voltage can be prevented.</p> |
申请公布号 |
JPH0344721(A) |
申请公布日期 |
1991.02.26 |
申请号 |
JP19890180780 |
申请日期 |
1989.07.12 |
申请人 |
TOSHIBA CORP |
发明人 |
KAMIMURA TOSHIYUKI;KAGEYAMA SEIICHI |
分类号 |
G06F1/28;G06F1/26;G06F12/16 |
主分类号 |
G06F1/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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