发明名称 A/D CONVERSION CIRCUIT
摘要 <p>PURPOSE:To reduce the cost and to attain multi-bit of an A/D converter by providing 4-value levels VH1-VH4, VL1-VL4 equal to each other to reference voltages VH, VL and switching a binary level for each of even and odd order number fields for each horizontal period. CONSTITUTION:The reference voltages VH, VL are switched alternately for each blanking period of one horizontal period in 4N-field from VH1,VL1 into VH3, VL3. The phase is inverted in the (4N+2) field and the reference voltages are switched alternately from VH3, VL3 into VH1, VL1. On the other hand, the phase is inverted in the (4N+1) field and the reference voltages are switched alternately from VH2, VL2 into VH4, VL4. The phase is inverted in the (4N+3) field and the reference voltages are switched alternately from VH4, VL4 into VH2, VL2. Thus, an output of M+2 bit is obtained in a pseudo way in time division by an N-bit A/D converter, a problem of flicker is solved and a low cost and multi-bit A/D converter is formed.</p>
申请公布号 JPH0338184(A) 申请公布日期 1991.02.19
申请号 JP19890173510 申请日期 1989.07.05
申请人 SEIKO EPSON CORP 发明人 SUZUKI MASAYUKI
分类号 H04N19/00;H03M1/12;H04N5/14;H04N19/85 主分类号 H04N19/00
代理机构 代理人
主权项
地址