发明名称 |
ENCODER, DECODER AND DATA CONVERTER HAVING THE SAME |
摘要 |
<p>PURPOSE:To reduce the circuit scale and the processing quantity by constituting the device such that the horizontal direction signal is synthesized at the final stage. CONSTITUTION:A data split and coded into 4 bands is written in a buffer memory 15 via an address switching circuit 3 with an address of a write address generating circuit 2. As to LL and LH bands, a vertical interpolation high frequency processing circuit 6 applies vertical interpolation. The data subjected to interpolation processing is added by an adder circuit 7 and written in the memory 15. The data read from the memory 15 is interpolated respectively by a horizontal interpolation low frequency processing circuit 12 and a horizontal interpolation high frequency processing circuit 13 respectively, added by the circuit 7 and outputted to a display device 14. Then the output is given to the device 14 while applying synthesis processing and a memory of full size is not required, and then the circuit scale and th processing quantity are reduced.</p> |
申请公布号 |
JPH0327687(A) |
申请公布日期 |
1991.02.06 |
申请号 |
JP19890160754 |
申请日期 |
1989.06.26 |
申请人 |
HITACHI LTD;HITACHI VIDEO ENG CO LTD |
发明人 |
YASUOKA MASAHIRO;NANAO HISASHI;KAWAI SATOSHI |
分类号 |
H04N19/00;H04N19/423;H04N19/426;H04N19/59;H04N19/63;H04N19/80 |
主分类号 |
H04N19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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