发明名称 |
MULTI-INPUT SIGNATURE REGISTER |
摘要 |
PURPOSE:To reduce a structural area of a register by making a feedback to an initial-stage exclusive OR gate from a last-stage delay element among a plurality of delay elements composing a linear feedback shift register to input a test train with the number of items thereof being odd. CONSTITUTION:Flip flops Di (i=1-n-1) are provided as delay elements the same in the number as signal lines of a test data. A feedback is made to a head exclusive OR gate 2 through a feedback loop 5 from a last-stage flip flop Dn-1. A test train with the number of items thereof being odd is inputted into a signature register thus arranged to allow the suppressing of error overlooking probability to about 1/2<n>. Thus, the structure of the signature regis ter can be minimized without lowering a capacity simply by adjusting the num ber of items of a test train to be inputted to an odd value. |
申请公布号 |
JPH0324482(A) |
申请公布日期 |
1991.02.01 |
申请号 |
JP19890158951 |
申请日期 |
1989.06.20 |
申请人 |
MITSUBISHI ELECTRIC CORP |
发明人 |
HIRATO HIRONORI;KOREMATSU JIRO |
分类号 |
G01R31/28;G01R31/319;G06F11/22 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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