发明名称 VARIABLE LENGTH ENCODING AND DECODING SYSTEM
摘要 <p>PURPOSE:To reduce the deviation of information occupied quantity between each buffer memory by adjusting write information on each buffer memory to perform the connection control of each buffer memory corresponding to the information occupied quantity of each buffer memory. CONSTITUTION:A write buffer memory selection part 21 which selects the buffer memories of (n) layers for encoder parts 4-1 to 4-n of (n) layers corresponding to the information occupied quantity of each of the buffer memories 5-1 to 5-n, and obtains the appropriate information occupied quantity of each buffer memory, and a selection state storage part 22 which stores the above selection states are provided. Also, a readout buffer memory selection part 23 which sends digital data read out from the buffer memories of (n) layers corresponding to the selection state of the selection state storage part 22 after re-arranging to prescribed sequence of the layer is provided. In such a way, it is possible to reduce the deviation of the state occupied quantity of the buffer memory made into (n) Iayers, therefore, to improve the working efficiency of the buffer memory.</p>
申请公布号 JPH0323720(A) 申请公布日期 1991.01.31
申请号 JP19890156690 申请日期 1989.06.21
申请人 FUJITSU LTD 发明人 HAMANO TAKASHI;SAKAI KIYOSHI;MATSUDA KIICHI
分类号 H04N19/15;G06F5/00;G06F5/16;H03M7/40;H04N7/24;H04N19/00;H04N19/124;H04N19/13;H04N19/196;H04N19/44;H04N19/503;H04N19/85;H04N19/91 主分类号 H04N19/15
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