| 摘要 |
A speech synthesizing apparatus includes an interpolation pitch calculation circuit wherein an interpolation pitch is calculated at every frame periods based upon a speech parameter. Specifically, a difference between a target value and a present value is stored in a shift register of 16 bits, and then, in order to omit the figures below the first place of decimals and to divide the difference by the number of subframes, the shift register is shifted rightward by 7 bits. If a numeral value of the shift register is negative, "1" is added to the number of units of the numeral value in an adding circuit such that an absolute value of the numeral value becomes smaller. When the numeral value of the shift register is positive, the numeral value outputted from the shift register is set in an interpolation pitch register as it is and, when negative, an output of the adding circuit is set in the interpolation pitch register.
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