| 摘要 |
<p>PURPOSE:To attain switching without replacing the sequence of simultaneous input packets by adopting multi-module configuration for the packet exchange system and providing a buffer to an outgoing line. CONSTITUTION:Packets P4, P3, P1 are inputted in this order to a switching circuit 6 of a buffer module and an input delay time D of the packet P3 with respect to the packet P4 is generated because a sorting module is passed by one stage. Moreover, the packet P1 arrives similarly with a time delay of 2D with respect to the packet P4. Thus, a controller 9 applies switch control to the switch circuit 6 so that this contention packet group is stored sequentially tn the order of an FIFO buffer 72. That is, the packets P4, P3, P1 are stored respectively in the FIFO buffers 72, 73, 71. Thus, the packets are outputted to an outgoing line 108 in the stored order by a selector 8 and the contention packets P4, P3, P1 are outputted to a desired outgoing line smoothly.</p> |
