| 摘要 |
A vector processor which maintains synchronization with an associated CPU by limiting the operational instruction proceedings. The vector processor utilizes an instruction register to store instructions from the CPU logical operations circuitry word processing in parallel with the CPU in accordance with instructions from the instruction register and a counter which increases in response to a start instruction from the CPU and decreases in response to the completion of an operation by the logical operation circuitry. A restraining signal is generated in response to a prescribed count of the counter, which delays the execution of the microprogram by the CPU. An indicator device is used for indicating storage of an instruction in the instruction register and a flag device is set in response to a start instruction from the CPU which actuates the indicator means even if no instruction is stored in the instruction register. A decision circuit is utilized to determine in response to a prescribed count of the counter whether or not the execution of the microprogram by the CPU is restrained. If it is determined that the execution is not restrained the decision circuitry actuates the indicator device in response to a start instruction from the CPU without setting the flag device. A start instruction for instructing the start of processing by the logical operation circuitry is generated in response to an indication by the indicator device. A detector circuit is utilized to detect a decrease in the counter and to prevent the execution of a restraining signal.
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