| 摘要 |
<p>An ECL to TTL translator (10) converts a signal from ECL logic levels to TTL compatible logic levels without introducing current spikes in the output signal during logic transitions. The ECL input signal (12, 14) is transformed into first and second differentially related currents which develop first and second voltages at two nodes (28, 36) for biasing first (30, 44, 46) and second (34, 48, 50) switching circuits which in turn generate first and second complementary control signals. The sum total of the differentially related currents are limited to a predetermined magnitude blocking simultaneously assertion of the control signals. An output stage (56, 58, 60, 62, 64, 66) includes upper (56, 58) and lower (60) transistors each responsive to the first and second control signal respectively for developing a TTL high and TTL low output signal. The first and second switching circuits inhibit simultaneous conduction of the upper and lower transistors of the output stage preventing undesirable current spikes in the output signal thereof.</p> |
