| 摘要 |
A synchronizing circuit for synchronizing the phase of a clock signal to the phase of a received digital signal includes a phase monitoring circuit for detecting, during each bit period of the digital signal, the phase advance of delay of the clock signal relative to the digital signals. A phase signal is outputting which is indicative of the phase advance or delay of the clock signal. A phase control circuit responds to the phase signal to either advance, delay or leave unchanged the phase of the clock signal with respect to the received digital signal. An inhibiting circuit coupled to the phase control circuit operates to prevent the phase control circuit from reversing the sense of the phase adjustment from advance to delay or from delay to advance in consecutive bit positions, interposing instead one bit position during which the phase of the clock signal is left unadjusted. |
