| 摘要 |
<p>A semiconductor memory device comprising memory cells (M11 to Mmn) for storing binary data, and first dummy cells (DM11 to DMm1) and second dummy cells (DM12 to DMm2) corresponding to the two storage conditions of the above memory cells, wherein the storage conditions of the memory cells are compared with those of the dummy cells by first and second sense amplifiers (1, 2), and the outputs of the two sense amplifiers are compared by a third sense amplifier (3) to detect the data stored in the memory cells. This makes it possible to provide a high-speed memory device which has a reduced number of memory cells, which is highly integrated, and which develops little reading error.</p> |
