| 摘要 |
<p>Disclosed herewith is a shiftregister for shifting data in series in synchronism with a shift clock signal and is composed of a plurality of data-shift sgages connected in cascade, each of which includes a shift-in terminal and a shift-out terminal, and each of which further includes a first transfer gate, a first data hold circuit, a second transfer gate and a second data hold circuit connected in this order between the shift-in and shift-out terminals. Further provided in each of the data-shift stages is a gate circuit, in particular a NOR gate, which responds to logic levels at selected ones of the respective circuit connection points and produces a pulse signal.</p> |
