| 摘要 |
<p>PURPOSE:To expand the high frequency limit of a treated frequency by amplifying, multiplying a timing signal by N, branching the resulting signal into two, inputting one signal to a logic circuit via a delay circuit and applying OR processing with a timing component extracted coarsely. CONSTITUTION:The output signal of a narrow band amplifier 5 is branched into two and inputted to a limiter amplifier 6 and a broad band amplifier 14. An output signal from the amplifier 6 is amplified by the multiple of N and an N multiplying circuit 17 with a frequency f0 synchronously with a reception signal inputted to an input terminal 9. The f0 clock signal outputted from the circuit 17 is branched into two, one is inputted to a delay circuit 13, where the signal is subjected to a prescribed delay, the resulting is fed to an OR circuit 11. Thus, the f0 clock signal as the output signal from the circuit 11 as the result of ORing the stable f0 clock signal inputted from the circuit 13 coarse f0 component clock signal from the 1st timing extraction filter 18 is outputted. The branched other signal is inputted to an identification circuit 7.</p> |
