| 摘要 |
A latch circuit which is resistant to electrostatic discharge includes four cross-coupled NOR gate pairs located in the four corners of an integrated circuit chip, and a fifth cross-coupled NOR gate pair positioned generally in the center of the integrated circuit chip. The Q outputs, the Q outputs, the reset inputs, and the set inputs of each of the five cross-coupled NOR gate pairs are connected together such that a single cross-coupled NOR gate pair receiving an electrostatic discharge will be held in its present state by the action of the other four cross coupled NOR gate pairs which will either supply current or sink current in order to maintain the state of the Q and Q-bar outputs.
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