Dram nonvolatizer

摘要

A nonvolatile memory subsystem includes DRAMs and a battery-backed controller chip. The controller chip monitors the system power supply level to ascertain power fault conditions. When a power fault is detected, the controller provides the DRAMs with both a regulated supply voltage and appropriately timed refresh signals. After the system power supply has returned to specification, the controller continues to generate refresh control signals until the commands it to stop.