Plesiochronous digital sequence stuffing clock signal extn. method - using bistable counter driven by delayed system clock which is ineffective during active control signal

摘要

Three counters (Z1-Z3) and a delay circuit (TL) are used to derive a working clock signal (TA), time-selective signals (Ts) and control signals (St) from the system clock (To). The first counter (Z1) divides the system clock frequency by n to obtain the working clock (TA), within whose period a number (m) of repetitive time-selective signals (Ts) appear. The second counter (Z2) produces control signals (St) at all time-selective clock instants for periodic frame build-up. The third counter (Z3) driven by the delayed system clock (To') gives the desired clocking output (LT). ADVANTAGE - Suitable for high bit rates.