| 摘要 |
PURPOSE: To properly display an 'unaccurate result' condition in accordance with its reference by providing plural registers holding a divisor, a dividend, and a partial dividend, a single end-around carry adder coupled to them, and an end-around carry propagation adder and sequencing the divisor to generate two quotient bits in each repeat. CONSTITUTION: A floating-point register 14 sends information received through a data storage bus 12 to an FA register 16, an FB register 18, or an FC register 22. A multiple selector 24 is a logic circuit, which generates multiples of a multi-plicand of multiplication or those of a divisor of division, and includes a logic circuit which realizes a matrix of multiples which can be used as divisor multiples in each repeat of the division sequence. Multiples are taken which are not equal to 3/4 of values obtained by dividing the dividend by the divisor with respect to all values of the divisor and the dividend within the range of the related most significant bit. Thus, the 'unaccurate result' condition is properly displayed. |
