| 摘要 |
PURPOSE: To improve the line drawing performance or a display device by providing a logic circuit which decodes a specific instruction which defines the operation of first and second values or that of first and third values and determining selection of the second or third value by a processor in accordance with the state of a processor condition code. CONSTITUTION: Contents of registers R1 and R2/R3 are stored in a general register array 30, and the processor condition code is stored in a processor condition register(PCR) 34. Contents of selected registers (R1 and R2 or R3) are supplied to an arithmetic logic unit 37 through lines 35 and 36 and are added there. The processor condition register 34 is updated in accordance with the operation result of the ALU 37 by a conventional method indicated by a route 38. The output of the ALU 37 determines a new error term of following repetition, and it is stored in the register R1. Thus, the processing performance of a repetitive task for line drawing or the like in a graphics device is improved. |
