| 摘要 |
The invention is preferably used in testing complex digital circuits, particularly if several different clock signals are used in these circuits. The proposed arrangement has data inputs and a shift data input, data outputs and a shift data output and clock and control signal inputs. It contains a flip-flop arrangement of two or three clocked latches which can be connected together to form a scan path, the first latch being preceded by a multiplexer, the data inputs of which are connected to the inputs of the arrangement. A circuit clock, a test clock and a circuit clock suppression signal are connected to a logic network combining the said signals, at the output of which network a generated control clock is present. The circuit clock suppression signal is also applied to the control input of the multiplexer. The clock inputs of the first and second latch are mutually negated at the control clock, the clock input of a third latch is connected to the circuit clock suppression signal. Certain outputs of the latches form the outputs of the arrangement. Design variants of the flip-flop arrangement as master/slave flip- flop or latch arrangement optionally designed for the testing of stuck-open faults, are specified. |
