| 摘要 |
<p>PURPOSE:To output a series of signal patterns scarcely having a time base error by providing a free running counter, an input capture register, etc., and storing time difference data into a comparison data register. CONSTITUTION:When an edge of an input signal applied to external signal input terminals 30 - 37 arrives, count data of a free running counter (FRC) 1000 of that time point is stored in a specific register in an input capture regis ter (ICR) 900. Accordingly, an exact arrival time point of the input signal can be confirmed by a software, and time difference data to a target time point for starting to send out an output signal having a series of signal patterns from an output port 1100 is sent out to a data bus 1200. This time difference data is stored in a comparison data register, and by storing the data to be outputted into a master latch through a bus 1200 at every stored set time, a series of signal patterns scarcely having a time base error can be outputted.</p> |
