| 摘要 |
<p>A field effect transistor having a difference in levels involving an upper main surface (35a), a wall surface (35b) and a lower main surface (35c) on the base layer (33). On the wall surface (35a) a gate insulating film (39) and a gate electrode (41) are vertically formed in this order. The film (39) and the electrode (41) extend between the upper and lower main surfaces (35a) and (35c). Both sides of the film (39) and the electrode (41) are impurity diffusion regions for forming source/drain regions (43) and (45). Since the gate electrode (41) whose gate width needs to be rather large is perpendicular to the base layer (33), larger scale integration can be realized.</p> |
