| 摘要 |
PURPOSE:To prevent malfunction due to a spike noise occurring by switching a clock signal by latching a PN code generated at a PN code generator by a clock signal having a phase difference with the clock signal to be supplied to the PN code generator, and outputting either one of them by a data selector. CONSTITUTION:The clock signal CLK is supplied to D flip-flops D1-D10 as the clock signal, and also, is inverted at an inverter 6, and is supplied to a D flip- flop 4 as a latch clock, and latches the PN code outputted from a shift register 2. The data selector 5 selects the PN code outputted from the shift register 2 when a dither clock signal DITCK is set at logic '1', and selects the PN code latched at the D flip-flop 4 when the dither clock signal DITCK is set at logic '0'. Thus, since no switching of the clock signal CLK and the clock signal inverted at the inverter 6 is performed, no spike noise generated at the time of switching in an on-going system occurs. |
