| 摘要 |
<p>PURPOSE:To simplify the constitution by using a single data buffer so as to transfer a data between communication interface control circuits. CONSTITUTION:A received data RD selected by a selector 4 is fed to an FIFO buffer 2 and a received clock RCK is fed to one input of an AND gate 5. A reception enable signal REN is fed to other input of the AND gate 5, then it output is fed to the FIFO buffer 2 as a shift-in clock Sin. The FIFO buffer 2 receives the received data RD sequentially synchronously with the shift-in clock Sin and outputs the data sequentially synchronously with a shift-out clock Sout. A transmission control section 7 generates a transmission enable signal TEN 2 when a reception control section 6 selects the relay direction from a communication interface control circuit 1a to 1b and generates a transmission enable signal TEN 1 when the section 6 selects the opposite relay direction.</p> |
