发明名称 TEST CIRCUIT FOR INTEGRATED CIRCUIT
摘要 PURPOSE:To suppress as much as possible the increase of the number of terminals of an integrated circuit(IC) test circuit by sending the internal state data on an internal IC obtained after the operating of the IC to an input/output terminal group via a tristate buffer group with use of the input/output control signal. CONSTITUTION:A signal of 'H' is inputted to a selection signal input terminal 8 together with application of a latch pulse in a state where the test mode setting data are inputted to the input/output terminals 1A - 1H. Thus the test mode setting data are held by a 2nd latch group 5. As a result, the operating result of an internal IC 6, i.e., the internal state data showing the internal states of the IC 6 obtained after the IC 6 operated based on the control data and the test mode setting data are outputted from the IC 6. Under such conditions, a signal of 'H' is inputted to an input/output control signal input terminal 7 to secure conduction of the tristate buffers 3A - 3H. Thus the test results are obtained through the terminals 1A - 1H and compared with the normal value to check whether the IC 6 is normally operating or not.
申请公布号 JPH02277143(A) 申请公布日期 1990.11.13
申请号 JP19890099704 申请日期 1989.04.18
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HIROTA MASAYUKI
分类号 G06F11/22 主分类号 G06F11/22
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