| 摘要 |
PURPOSE:To attain rapid processing even when plural timing patterns are used by dividing a pattern memory into plural blocks and accessing respective blocks. CONSTITUTION:The imaging circuit is provided with the pattern memory 8 for storing the timing pattern of each block to be a paint-out imaging area, a logical circuit for calculating AND between data indicating the painting-out area and the data of the pattern memory 8, a control circuit 3 for controlling the writing/reading of the frame buffer memory 4 and the pattern memory 8, and an address forming circuit 9 for forming the addresses of the pattern memory 8 from input addresses and input data so as to divide the pattern memory 5 into plural blocks and access the pattern memory 8. Consequently, respective blocks can be processed as if the blocks are mapped on the whole memory and the painting-out of plural timing patterns can be rapidly executed. |
