| 摘要 |
<p>The device synchronises a pseudo-binary signal (HDB +), which is particularly affected by high jitter, with a clock signal (HRG) regenerated as a synchronised signal (HB +). The device can be included between an output of a bipolar-binary converter receiving a plesiochronous bipolar signal and an input of an HDB/binary transcoder in a circuit for synchronising a time-division multiplexer. The clock signal has a period Tj substantially less than the nominal period of the pseudo-binary signal and offers phase hops, lying in particular between Tj/2 and Tj, so that the clock signal has an average period equal to the nominal period. The device preferably comprises, at input, a flip-flop (91) used as a frequency divider-by-2 in order to produce a first logic signal (H +) with alternately "0" and "1" logic levels in response to "0" to "1" transitions in the pseudo-binary signal, and then a flip-flop (92) for setting the transitions in the first logic signal (H +) in phase with active "0" to "1" transitions of the clock signal into an in-phase logic signal (H + (i)), and two flip-flops (93, 94) and an exclusive-OR gate (95) for providing the synchronised signal (HB +) with gating pulses at the "1" level having a width equal to the period of the clock signal and set up respectively in response to the transitions of the in-phase signal (H + (i)). <IMAGE></p> |
