HANDOTAIKIOKUSOCHI

摘要

A first transistor (59) is connected between each of data sensing means and VDD power source. A second transistor (60) is connected between each of data sensing means and ground. A control signal to control the active state of each data sensing means (50) is directly applied to the gate of the first transistor. The control signal is applied to the gate of the second transistor, with a time delay corresponding to that by a word line (32). The timing of rendering each data sensing means active in state is substantially coincident with the optimum timing of a potential change on each correspond ing bit line (12, 14).