| 摘要 |
A high speed data packet switching circuit has a software controlled primary processing unit (12), a plurality of network interface units (40a-40n) connected to a plurality of networks for receiving incoming data packet streams and for transmitting outgoing data packet streams, a plurality of high speed data stream hardware control circuits (14a-14p) for processing data packets in response to instructions from the primary processing unit (12) and circuitry for interconnecting the primary processing unit (12), the interface units (40a-40n), and the data stream control circuits (14a-14p). The primary processing unit (12), receives from the network interface unit (40a-40n) at least a first one of the data packets of each new data packet stream and assigns that stream to be processed by one of the data stream control circuits (14a-14p) without further processing by the primary processing unit (12). The apparatus and method thus perform routine, repetitive processing steps on the further packets of the data stream using the high speed hardware (14a-14p), while the initial processing and other non-repetitive or special processing of the data packets are performed in software. Particular hardware is described for effecting the high speed hardware processing of the data packets. |
