| 摘要 |
PURPOSE:To allow the PLL circuit to follow a timing pulse in a short time even when the timing pulse is inputted in a same frequency by keeping the oscillation of the clock frequency just before an input timing pulse is lost in the PLL circuit. CONSTITUTION:A couple of noninverting and inverting clocks 501, 502 are generated from an output of a VCO 4 and the phase of the clocks and that of an input timing pulse 101 are compared. Then charge/discharge current control pulses 301, 302 are obtained and they are fed to a smoothing circuit 3. When the input timing pulse 101 is lost, the time of charge/discharge control pulses 301, 302 is made coincident. The charge/discharge time is coincident, a mean value of a smoothing circuit 303 is unchanged and the output of a VCO 4 keeps a constant value for the said period. Thus, even when the input timing pulse 101 is lost, the circuit keeps oscillating the clock frequency equal to that just before and the circuit follows in a short time at the input of the succeeding timing pulse. |
